This invention relates generally to instruction set extensions for increased code density. In particular the invention relates to encapsulating long instructions from a full instruction set into a set of short instructions.
Reduced instruction set computing (RISC) processors typically have a fixed bit-width instruction size. Common sizes are 16-bits and 32-bits. 32-bits give flexibility in expressing instructions and operands but at the expense of typically larger code size than the 16-bit instruction sets.
Known reduced instruction sets consist of a subset of the full instruction set. In particular often these reduced instruction sets exclude any instructions which are longer than 16 bits. Reduced instruction sets therefore consist of the more simple (low level) instructions of the full instruction sets.
A problem with reduced instruction sets is that some specific (high level) instructions for which the hardware of a processor might be optimised cannot be expressed in short instructions because they are longer than the length of a short instruction. An example of such a specific instruction is a Fast Fourier Transform instruction which the hardware of a digital signal processor (DSP) might be optimised to execute. In such cases a combination of low level, fundamental instructions may be able to produce the same result as the specific instruction. However, because many low level instructions will need to be executed to achieve the same result as the specific instruction, the operation will be much slower than if long instructions had been used.
Another problem with the use of reduced instruction sets is that a separate compiler must be designed and manufactured for the reduced instruction set as compared to the compiler that is used for the corresponding long instruction set. This delays the time in between developing the reduced instruction set and being able to make chips available to the market which use the reduced instruction set.
Some existing processors (for example those developed by ARM and MIPS) are able to execute both (i) full instruction sets which use long instructions, and (ii) reduced instruction sets which use short instructions. This functionality enables long instructions to be used for specific high-level instructions, and otherwise short instructions to be used. However, these processors are complex because they must be able to receive and process both full instruction sets and reduced instruction sets.
There is a need for a method of assembling instruction sets which enables fast processing of both low-level fundamental instructions and high-level specific instructions whilst not significantly increasing complexity.